SystemVerilog assertion debugging: A visualization and pattern matching model

Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky. SystemVerilog assertion debugging: A visualization and pattern matching model. In IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2015, Victoria, BC, Canada, August 24-26, 2015. pages 385-390, IEEE, 2015. [doi]

@inproceedings{MostafaSED15,
  title = {SystemVerilog assertion debugging: A visualization and pattern matching model},
  author = {Moaz Mostafa and Mona Safar and M. Watheq El-Kharashi and Mohamed Dessouky},
  year = {2015},
  doi = {10.1109/PACRIM.2015.7334867},
  url = {https://doi.org/10.1109/PACRIM.2015.7334867},
  researchr = {https://researchr.org/publication/MostafaSED15},
  cites = {0},
  citedby = {0},
  pages = {385-390},
  booktitle = {IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2015, Victoria, BC, Canada, August 24-26, 2015},
  publisher = {IEEE},
  isbn = {978-1-4673-7788-1},
}