SystemVerilog assertion debugging: A visualization and pattern matching model

Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky. SystemVerilog assertion debugging: A visualization and pattern matching model. In IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2015, Victoria, BC, Canada, August 24-26, 2015. pages 385-390, IEEE, 2015. [doi]

Abstract

Abstract is missing.