An on-chip parallel memory architecture for a stereo vision system

Andy Motten, Luc Claesen. An on-chip parallel memory architecture for a stereo vision system. In 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010. pages 495-498, IEEE, 2010. [doi]

@inproceedings{MottenC10-0,
  title = {An on-chip parallel memory architecture for a stereo vision system},
  author = {Andy Motten and Luc Claesen},
  year = {2010},
  doi = {10.1109/ICECS.2010.5724557},
  url = {http://dx.doi.org/10.1109/ICECS.2010.5724557},
  researchr = {https://researchr.org/publication/MottenC10-0},
  cites = {0},
  citedby = {0},
  pages = {495-498},
  booktitle = {17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010},
  publisher = {IEEE},
  isbn = {978-1-4244-8155-2},
}