Optimizing wiring space in slicing floorplans

J. T. Mowchenko, Y. Yang. Optimizing wiring space in slicing floorplans. In 5th Great Lakes Symposium on VLSI (GLS-VLSI 95), March 16-18, 1995, The State University of New York at Buffalo, USA. pages 54, IEEE Computer Society, 1995. [doi]

Authors

J. T. Mowchenko

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Y. Yang

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