J. T. Mowchenko, Y. Yang. Optimizing wiring space in slicing floorplans. In 5th Great Lakes Symposium on VLSI (GLS-VLSI 95), March 16-18, 1995, The State University of New York at Buffalo, USA. pages 54, IEEE Computer Society, 1995. [doi]
@inproceedings{MowchenkoY95,
title = {Optimizing wiring space in slicing floorplans},
author = {J. T. Mowchenko and Y. Yang},
year = {1995},
url = {http://csdl.computer.org/comp/proceedings/glsvlsi/1995/7035/00/70350054abs.htm},
tags = {optimization, slicing},
researchr = {https://researchr.org/publication/MowchenkoY95},
cites = {0},
citedby = {0},
pages = {54},
booktitle = {5th Great Lakes Symposium on VLSI (GLS-VLSI 95), March 16-18, 1995, The State University of New York at Buffalo, USA},
publisher = {IEEE Computer Society},
}