Parallel optimization of transistor level circuits using cartesian genetic programming

Vojtech Mrazek, Zdenek Vasícek. Parallel optimization of transistor level circuits using cartesian genetic programming. In Peter A. N. Bosman, editor, Genetic and Evolutionary Computation Conference, Berlin, Germany, July 15-19, 2017, Companion Material Proceedings. pages 1849-1856, ACM, 2017. [doi]

Authors

Vojtech Mrazek

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Zdenek Vasícek

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