Vojtech Mrazek, Zdenek Vasícek. Parallel optimization of transistor level circuits using cartesian genetic programming. In Peter A. N. Bosman, editor, Genetic and Evolutionary Computation Conference, Berlin, Germany, July 15-19, 2017, Companion Material Proceedings. pages 1849-1856, ACM, 2017. [doi]
@inproceedings{MrazekV17,
title = {Parallel optimization of transistor level circuits using cartesian genetic programming},
author = {Vojtech Mrazek and Zdenek Vasícek},
year = {2017},
doi = {10.1145/3067695.3084212},
url = {http://doi.acm.org/10.1145/3067695.3084212},
researchr = {https://researchr.org/publication/MrazekV17},
cites = {0},
citedby = {0},
pages = {1849-1856},
booktitle = {Genetic and Evolutionary Computation Conference, Berlin, Germany, July 15-19, 2017, Companion Material Proceedings},
editor = {Peter A. N. Bosman},
publisher = {ACM},
isbn = {978-1-4503-4939-0},
}