Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip

Sayed Taha Muhammad, Magdy A. El-Moursy, Ali A. El-Moursy, Hesham F. A. Hamed. Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip. J. Parallel Distrib. Comput., 102:175-185, 2017. [doi]

Abstract

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