Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression

Hannes Muhr, Roland Höler. Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression. In Georgi Gaydadjiev, C. John Glossner, Jarmo Takala, Stamatis Vassiliadis, editors, Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006. pages 123-127, IEEE, 2006. [doi]

Abstract

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