1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors - researchr publication authors

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Chhandak Mukherjee, Cristell Maneux, Julien Pezard, Guilhem Larrieu. 1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors. In 47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, September 11-14, 2017. pages 34-37, IEEE, 2017. [doi]

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