Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy. Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. pages 224-229, IEEE Computer Society, 2005. [doi]
Abstract is missing.