Gwonhan Mun, Kunseok Kang, Deaho Kim. Timing diagram for CNPC interleaver implementation on FPGA. In International Conference on Artificial Intelligence in Information and Communication, ICAIIC 2021, Jeju Island, South Korea, April 13-16, 2021. pages 381-384, IEEE, 2021. [doi]
@inproceedings{MunKK21,
title = {Timing diagram for CNPC interleaver implementation on FPGA},
author = {Gwonhan Mun and Kunseok Kang and Deaho Kim},
year = {2021},
doi = {10.1109/ICAIIC51459.2021.9415266},
url = {https://doi.org/10.1109/ICAIIC51459.2021.9415266},
researchr = {https://researchr.org/publication/MunKK21},
cites = {0},
citedby = {0},
pages = {381-384},
booktitle = {International Conference on Artificial Intelligence in Information and Communication, ICAIIC 2021, Jeju Island, South Korea, April 13-16, 2021},
publisher = {IEEE},
isbn = {978-1-7281-7638-3},
}