Timing diagram for CNPC interleaver implementation on FPGA

Gwonhan Mun, Kunseok Kang, Deaho Kim. Timing diagram for CNPC interleaver implementation on FPGA. In International Conference on Artificial Intelligence in Information and Communication, ICAIIC 2021, Jeju Island, South Korea, April 13-16, 2021. pages 381-384, IEEE, 2021. [doi]

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