Yakup Murat. Key Architectural Optimizations for Hardware Efficient JPEG-LS Encoder. In IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018. pages 243-248, IEEE, 2018. [doi]
@inproceedings{Murat18,
title = {Key Architectural Optimizations for Hardware Efficient JPEG-LS Encoder},
author = {Yakup Murat},
year = {2018},
doi = {10.1109/VLSI-SoC.2018.8644996},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644996},
researchr = {https://researchr.org/publication/Murat18},
cites = {0},
citedby = {0},
pages = {243-248},
booktitle = {IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
publisher = {IEEE},
isbn = {978-1-5386-4756-1},
}