Petri net modeling of gate and interconnect delays for power estimation

Ashok K. Murugavel, N. Ranganathan. Petri net modeling of gate and interconnect delays for power estimation. In Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002. pages 455-460, ACM, 2002. [doi]

Authors

Ashok K. Murugavel

This author has not been identified. Look up 'Ashok K. Murugavel' in Google

N. Ranganathan

This author has not been identified. Look up 'N. Ranganathan' in Google