8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications

James Myers, Anand Savanth, David Howard, Rohan Gaddh, Pranay Prabhat, David Flynn. 8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015. pages 1-3, IEEE, 2015. [doi]

Authors

James Myers

This author has not been identified. Look up 'James Myers' in Google

Anand Savanth

This author has not been identified. Look up 'Anand Savanth' in Google

David Howard

This author has not been identified. Look up 'David Howard' in Google

Rohan Gaddh

This author has not been identified. Look up 'Rohan Gaddh' in Google

Pranay Prabhat

This author has not been identified. Look up 'Pranay Prabhat' in Google

David Flynn

This author has not been identified. Look up 'David Flynn' in Google