High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit - researchr publication authors

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Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu. High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. In 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA. pages 70-75, IEEE Computer Society, 2008. [doi]

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