Table of Contents

• EDA to the Rescue of the Silicon RoadmapThomas W. Williams. 1 [doi]
• A Mature Methodology for Implementing Multi-Valued Logic in SiliconMark H. Nodine, Craig M. Files. 2-7 [doi]
• Design of High-Performance Quaternary Adders Based on Output-Generator SharingHirokatsu Shirahama, Takahiro Hanyu. 8-13 [doi]
• Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR DevicesAkihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu. 14-19 [doi]
• Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued DataYasushi Yuminaka, Yasunori Takahashi. 20-25 [doi]
• Betweenness, Metrics and Entropies in LatticesDan A. Simovici. 26-31 [doi]
• On Maximal Hyperclones on {0, 1} — A New ApproachHajime Machida, Jovanka Pantovic. 32-37 [doi]
• Majority and Other Polynomials in Minimal ClonesHajime Machida, Tamas Waldhauser. 38-43 [doi]
• Comparative Study by Solving the Test Compaction ProblemDoina Logofatu, Rolf Drechsler. 44-49 [doi]
• Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function GeneratorsShinobu Nagayama, Tsutomu Sasao. 50-56 [doi]
• On the Complexity of Classification FunctionsTsutomu Sasao. 57-63 [doi]
• MDD with Added Null-Value and All-Value EdgesCraig M. Files, Mark H. Nodine. 64-69 [doi]
• High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode CircuitTasuku Nagai, Naoya Onizawa, Takahiro Hanyu. 70-75 [doi]
• Permutations under Spectral TransformsClaudio Moraga. 76-81 [doi]
• On Fixed Points and Cycles in the Reed Muller DomainClaudio Moraga, Suzana Stojkovic, Radomir S. Stankovic. 82-87 [doi]
• A Galois Field Approach to Modelling Gene Expression RegulationHosam A. Aleem, Ferda Mavituna, David H. Green. 88-93 [doi]
• On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay FaultsStephan Eggersglüß, Rolf Drechsler. 94-99 [doi]
• Deciding the Satisfiability of Propositional Formulas in Finitely-Valued Signed LogicsVictor Chepoi, Nadia Creignou, Miki Hermann, Gernot Salzer. 100-105 [doi]
• Encoding Max-CSP into Partial Max-SATJosep Argelich, Alba Cabiscol, Inês Lynce, Felip Manyà. 106-111 [doi]
• High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description LanguageYuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi. 112-117 [doi]
• Semirigid Equivalence Relations on a Finite SetMasahiro Miyakawa, Maurice Pouzet, Ivo G. Rosenberg, Hisayuki Tatsumi. 118-123 [doi]
• Foundations of Higher Radix Numeric ComputationDavid W. Matula. 124 [doi]
• Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision DiagramMozammel H. A. Khan, Nafisa K. Siddika, Marek A. Perkowski. 125-130 [doi]
• A Qualitative Modal Representation of Quantum Register TransformationsAndrea Masini, Luca Viganò, Margherita Zorzi. 131-137 [doi]
• On the Data Structure Metrics of Quantum Multiple-Valued Decision DiagramsDavid Y. Feinstein, Mitchell A. Thornton, D. Michael Miller. 138-143 [doi]
• Superposed Quantum State Initialization Using Disjoint Prime Implicants (SQUID)David J. Rosenbaum, Marek A. Perkowski. 144-149 [doi]
• Generalized Modus Ponens Based on Linguistic Modifiers in a Symbolic Multi-Valued FrameworkSaoussen Bel Hadj Kacem, Amel Borgi, Khaled Ghédira. 150-155 [doi]
• Soft Computing Methods for Prediction of Replication Origins in CaudovirusesRaul Cruz-Cano, Igor N. Aizenberg. 156-162 [doi]
• Default Reasoning with Imperfect Information in Multivalued LogicsDaniel Stamate. 163-168 [doi]
• Classification of Fastest Quaternary Linearly Independent Arithmetic TransformsBogdan J. Falkowski, Cheng Fu. 169-173 [doi]
• A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital ConverterKazuki Akutagawa, Kazuya Machida, Takao Waho. 174-179 [doi]
• Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based CellsNobuaki Okada, Michitaka Kameyama. 180-185 [doi]
• Multiple Valued Logic Using 3-State Quantum Dot Gate FETsJohn A. Chandy, Faquir C. Jain. 186-190 [doi]
• Projective Measurement-Based Logic Synthesis of Quantum CircuitsMartin Lukac, Marek A. Perkowski. 191-196 [doi]
• Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical CellsTheodore W. Manikas, Dale Teeters. 197-201 [doi]
• Quantum Logic Implementation of Unary Arithmetic OperationsMitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller. 202-207 [doi]
• Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer CircuitsMozammel H. A. Khan. 208-213 [doi]
• Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don t CaresDaniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler. 214-219 [doi]
• RevLib: An Online Resource for Reversible Functions and Reversible CircuitsRobert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler. 220-225 [doi]
• Properties and Computational Algorithm for Fastest Quaternary Linearly Independent TransformsCicilia C. Lozano, Bogdan J. Falkowski, Tadeusz Luba. 226-231 [doi]
• Hybrid Reed-Muller Haar Transform and its Application in Reduction the Spectral Representations of Logic FunctionsSusanna Minasyan, Jaakko Astola, Karen O. Egiazarian, Radomir S. Stankovic. 232-237 [doi]
• Remarks on Bandwidth and Regularities in Functions on Finite Non-Abelian GroupsRadomir S. Stankovic, Jaakko Astola. 238-243 [doi]