Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance

Pradeep Nair, Savithra Eratne, Eugene B. John. Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance. J. Low Power Electronics, 8(4):464-471, 2012. [doi]

Abstract

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