A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector - researchr publication authors

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Hiroki Nakahara, Tsutomu Sasao. A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. In IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy. pages 1-5, IEEE, 2018. [doi]

This author has not been identified. Look up 'Hiroki Nakahara' in GoogleThis author has not been identified. Look up 'Tsutomu Sasao' in Google

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