Hiroki Nakahara, Tsutomu Sasao. A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. In IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy. pages 1-5, IEEE, 2018. [doi]
@inproceedings{NakaharaS18,
title = {A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector},
author = {Hiroki Nakahara and Tsutomu Sasao},
year = {2018},
doi = {10.1109/ISCAS.2018.8351850},
url = {https://doi.org/10.1109/ISCAS.2018.8351850},
researchr = {https://researchr.org/publication/NakaharaS18},
cites = {0},
citedby = {0},
pages = {1-5},
booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy},
publisher = {IEEE},
isbn = {978-1-5386-4881-0},
}