Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara. Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Transactions, 90-D(1):296-305, 2007. [doi]
@article{NakasatoOSF07,
title = {Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability},
author = {Masato Nakasato and Satoshi Ohtake and Kewal K. Saluja and Hideo Fujiwara},
year = {2007},
doi = {10.1093/ietisy/e90-1.1.296},
url = {http://dx.doi.org/10.1093/ietisy/e90-1.1.296},
tags = {testing},
researchr = {https://researchr.org/publication/NakasatoOSF07},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {90-D},
number = {1},
pages = {296-305},
}