Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability

Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara. Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Transactions, 90-D(1):296-305, 2007. [doi]

Abstract

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