Implementation of the compression function for selected SHA-3 candidates on FPGA

Ashkan Hosseinzadeh Namin, M. Anwar Hasan. Implementation of the compression function for selected SHA-3 candidates on FPGA. In 24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Workshop Proceedings. pages 1-4, IEEE, 2010. [doi]

@inproceedings{NaminH10,
  title = {Implementation of the compression function for selected SHA-3 candidates on FPGA},
  author = {Ashkan Hosseinzadeh Namin and M. Anwar Hasan},
  year = {2010},
  doi = {10.1109/IPDPSW.2010.5470742},
  url = {http://dx.doi.org/10.1109/IPDPSW.2010.5470742},
  researchr = {https://researchr.org/publication/NaminH10},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Workshop Proceedings},
  publisher = {IEEE},
}