High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis

Ashkan Hosseinzadeh Namin, Karl Leboeuf, Roberto Muscedere, Huapeng Wu, Majid Ahmadi. High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis. IET Circuits, Devices & Systems, 4(2):168-179, 2010. [doi]

Authors

Ashkan Hosseinzadeh Namin

This author has not been identified. Look up 'Ashkan Hosseinzadeh Namin' in Google

Karl Leboeuf

This author has not been identified. Look up 'Karl Leboeuf' in Google

Roberto Muscedere

This author has not been identified. Look up 'Roberto Muscedere' in Google

Huapeng Wu

This author has not been identified. Look up 'Huapeng Wu' in Google

Majid Ahmadi

This author has not been identified. Look up 'Majid Ahmadi' in Google