K. Namura, Johannes Maximilian Kühn, Tohru Adachi, H. Imachi, H. Kaneko, T. Kato, Go Watanabe, Naoto Tanaka, S. Kashihara, Hiroshi Miyashita, Y. Tomonaga, Ryosuke Okuta, Takuya Akiba, Brian Vogel, S. Kitajo, F. Osawa, K. Takahashi, Y. Takatsukasa, K. Mizumaru, T. Yamauchi, J. Ono, A. Takahashi, Tanvir Ahmed, Y. Doi, K. Hiraki, J. Makino. MN-Core - A Highly Efficient and Scalable Approach to Deep Learning. In 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021. pages 1-2, IEEE, 2021. [doi]
@inproceedings{NamuraKAIKKWTKM21,
title = {MN-Core - A Highly Efficient and Scalable Approach to Deep Learning},
author = {K. Namura and Johannes Maximilian Kühn and Tohru Adachi and H. Imachi and H. Kaneko and T. Kato and Go Watanabe and Naoto Tanaka and S. Kashihara and Hiroshi Miyashita and Y. Tomonaga and Ryosuke Okuta and Takuya Akiba and Brian Vogel and S. Kitajo and F. Osawa and K. Takahashi and Y. Takatsukasa and K. Mizumaru and T. Yamauchi and J. Ono and A. Takahashi and Tanvir Ahmed and Y. Doi and K. Hiraki and J. Makino},
year = {2021},
doi = {10.23919/VLSICircuits52068.2021.9492395},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492395},
researchr = {https://researchr.org/publication/NamuraKAIKKWTKM21},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021},
publisher = {IEEE},
isbn = {978-4-86348-780-2},
}