A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks

Govind Narasimman, Subhrajit Roy, Xuanyao Fong, Kaushik Roy 0001, Chip-Hong Chang, Arindam Basu. A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016. pages 914-917, IEEE, 2016. [doi]

Authors

Govind Narasimman

This author has not been identified. Look up 'Govind Narasimman' in Google

Subhrajit Roy

This author has not been identified. Look up 'Subhrajit Roy' in Google

Xuanyao Fong

This author has not been identified. Look up 'Xuanyao Fong' in Google

Kaushik Roy 0001

This author has not been identified. Look up 'Kaushik Roy 0001' in Google

Chip-Hong Chang

This author has not been identified. Look up 'Chip-Hong Chang' in Google

Arindam Basu

This author has not been identified. Look up 'Arindam Basu' in Google