Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS - researchr publication authors

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Siva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan. Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. In Vivek De, Mary Jane Irwin, Ingrid Verbauwhede, Christian Piguet, editors, Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002. pages 19-23, ACM, 2002. [doi]

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