Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs - researchr publication authors

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A. R. Naseer, M. Balakrishnan, Anshul Kumar. Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. In Will Moore, Wayne Luk, editors, Field-Programmable Logic and Applications, 5th International Workshop, FPL 95, Oxford, UK, August 29 - September 1, 1995, Proceedings. Volume 975 of Lecture Notes in Computer Science, pages 139-148, Springer, 1995.

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