A. R. Naseer, M. Balakrishnan, Anshul Kumar. Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. In Will Moore, Wayne Luk, editors, Field-Programmable Logic and Applications, 5th International Workshop, FPL 95, Oxford, UK, August 29 - September 1, 1995, Proceedings. Volume 975 of Lecture Notes in Computer Science, pages 139-148, Springer, 1995.
@inproceedings{NaseerBK95,
title = {Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs},
author = {A. R. Naseer and M. Balakrishnan and Anshul Kumar},
year = {1995},
tags = {rule-based},
researchr = {https://researchr.org/publication/NaseerBK95},
cites = {0},
citedby = {0},
pages = {139-148},
booktitle = {Field-Programmable Logic and Applications, 5th International Workshop, FPL 95, Oxford, UK, August 29 - September 1, 1995, Proceedings},
editor = {Will Moore and Wayne Luk},
volume = {975},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {3-540-60294-1},
}