Systolic Architecture for Computing the Discrete Fourier Transform on FPGAs

J. Greg Nash. Systolic Architecture for Computing the Discrete Fourier Transform on FPGAs. In 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings. pages 305-306, IEEE Computer Society, 2005. [doi]

@inproceedings{Nash05,
  title = {Systolic Architecture for Computing the Discrete Fourier Transform on FPGAs},
  author = {J. Greg Nash},
  year = {2005},
  doi = {10.1109/FCCM.2005.60},
  url = {http://doi.ieeecomputersociety.org/10.1109/FCCM.2005.60},
  tags = {architecture},
  researchr = {https://researchr.org/publication/Nash05},
  cites = {0},
  citedby = {0},
  pages = {305-306},
  booktitle = {13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-2445-1},
}