G. Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, A. D'Alessandro, L. De Santis, D. Di Cicco, W. Di Francesco, M. L. Gallese, G. Gallo, M. Incarnati, C. Lattaro, A. Macerola, G. G. Marotta, V. Moschiano, D. Orlandi, F. Paolini, S. Perugini, L. Pilolli, P. Pistilli, G. Rizzo, F. Rori, Massimo Rossini, G. Santin, E. Sirizotti, A. Smaniotto, U. Siciliani, M. Tiburzi, R. Meyer, A. Goda, B. Filipiak, Tommaso Vali, M. Helm, R. Ghodsi. A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology. In 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013. pages 218-219, IEEE, 2013. [doi]
@inproceedings{NasoBCCCCDSCFGGILMMMOPPPPRRRSSSSTMGFVHG13,
title = {A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology},
author = {G. Naso and L. Botticchio and M. Castelli and C. Cerafogli and M. Cichocki and P. Conenna and A. D'Alessandro and L. De Santis and D. Di Cicco and W. Di Francesco and M. L. Gallese and G. Gallo and M. Incarnati and C. Lattaro and A. Macerola and G. G. Marotta and V. Moschiano and D. Orlandi and F. Paolini and S. Perugini and L. Pilolli and P. Pistilli and G. Rizzo and F. Rori and Massimo Rossini and G. Santin and E. Sirizotti and A. Smaniotto and U. Siciliani and M. Tiburzi and R. Meyer and A. Goda and B. Filipiak and Tommaso Vali and M. Helm and R. Ghodsi},
year = {2013},
doi = {10.1109/ISSCC.2013.6487707},
url = {http://dx.doi.org/10.1109/ISSCC.2013.6487707},
researchr = {https://researchr.org/publication/NasoBCCCCDSCFGGILMMMOPPPPRRRSSSSTMGFVHG13},
cites = {0},
citedby = {0},
pages = {218-219},
booktitle = {2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4515-6},
}