Atul Prasad Deb Nath, Swarup Bhunia, Sandip Ray. ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies. In 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018. pages 411-416, IEEE Computer Society, 2018. [doi]
@inproceedings{NathBR18,
title = {ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies},
author = {Atul Prasad Deb Nath and Swarup Bhunia and Sandip Ray},
year = {2018},
doi = {10.1109/ISVLSI.2018.00081},
url = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2018.00081},
researchr = {https://researchr.org/publication/NathBR18},
cites = {0},
citedby = {0},
pages = {411-416},
booktitle = {2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018},
publisher = {IEEE Computer Society},
isbn = {978-1-5386-7099-6},
}