CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation

João Navarro Jr., Wilhelmus A. M. Van Noije. CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation. In 8th Great Lakes Symposium on VLSI (GLS-VLSI 98), 19-21 February 1998, Lafayette, LA, USA. pages 89-94, IEEE Computer Society, 1998. [doi]

Abstract

Abstract is missing.