Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques

Osama Neiroukh, Xiaoyu Song. Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. pages 294-299, IEEE Computer Society, 2005. [doi]

Abstract

Abstract is missing.