A Fault Tolerant Hierarchical Network on Chip Router Architecture

Mohammad Hossein Neishaburi, Zeljko Zilic. A Fault Tolerant Hierarchical Network on Chip Router Architecture. In 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011. pages 445-453, IEEE, 2011. [doi]

Abstract

Abstract is missing.