Decimal multiplier on FPGA using embedded binary multipliers - researchr publication

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Horácio C. Neto, Mário P. Véstias. Decimal multiplier on FPGA using embedded binary multipliers. In FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008. pages 197-202, IEEE, 2008. [doi]

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