Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations

José Luis Neves, Eby G. Friedman. Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. VLSI Signal Processing, 16(2-3):149-161, 1997. [doi]

Abstract

Abstract is missing.