Wing W. Y. Ng, Jiale Chen, Jiayi Zhang, Wen Li 0015, Meihua Liu. VERIMLA: A Unified Framework for Verilog Generation via Multi-Level Alignment and Formal Equivalence Verification. In IEEE International Symposium on Circuits and Systems, ISCAS 2026, Shanghai, China, May 24-28, 2026. pages 3734-3738, IEEE, 2026. [doi]
Abstract is missing.