A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation - researchr publication authors

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Meng Ni, Xiao Wang 0021, Fule Li, Zhihua Wang 0001. A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation. IEEE Trans. VLSI Syst., 29(7):1416-1427, 2021. [doi]

This author has not been identified. Look up 'Meng Ni' in GoogleThis author has not been identified. Look up 'Xiao Wang 0021' in GoogleThis author has not been identified. Look up 'Fule Li' in GoogleThis author has not been identified. Look up 'Zhihua Wang 0001' in Google

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