A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS - researchr publication authors

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Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi. A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012. pages 553-554, IEEE, 2012. [doi]

This author has not been identified. Look up 'Kiichi Niitsu' in GoogleThis author has not been identified. Look up 'Masato Sakurai' in GoogleThis author has not been identified. Look up 'Naohiro Harigai' in GoogleThis author has not been identified. Look up 'Daiki Hirabayashi' in GoogleThis author has not been identified. Look up 'Takahiro J. Yamaguchi' in GoogleThis author has not been identified. Look up 'Haruo Kobayashi' in Google

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