Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi. A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012. pages 553-554, IEEE, 2012. [doi]
@inproceedings{NiitsuSHHYK12,
title = {A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS},
author = {Kiichi Niitsu and Masato Sakurai and Naohiro Harigai and Daiki Hirabayashi and Takahiro J. Yamaguchi and Haruo Kobayashi},
year = {2012},
doi = {10.1109/ASPDAC.2012.6165014},
url = {http://dx.doi.org/10.1109/ASPDAC.2012.6165014},
researchr = {https://researchr.org/publication/NiitsuSHHYK12},
cites = {0},
citedby = {0},
pages = {553-554},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012},
publisher = {IEEE},
isbn = {978-1-4673-0770-3},
}