Power reduction techniques for Dynamically Reconfigurable Processor Arrays

Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsusmi, Vasutan Tunbunheng, Hideharu Amano. Power reduction techniques for Dynamically Reconfigurable Processor Arrays. In FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008. pages 305-310, IEEE, 2008. [doi]

Abstract

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