Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura. 7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. pages 132-133, IEEE, 2016. [doi]
@inproceedings{NoguchiITAKKHAS16,
title = {7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme},
author = {Hiroki Noguchi and Kazutaka Ikegami and Satoshi Takaya and Eishi Arima and Keiichi Kushida and Atsushi Kawasumi and Hiroyuki Hara and Keiko Abe and Naoharu Shimomura and Junichi Ito and Shinobu Fujita and Takashi Nakada and Hiroshi Nakamura},
year = {2016},
doi = {10.1109/ISSCC.2016.7417942},
url = {http://dx.doi.org/10.1109/ISSCC.2016.7417942},
researchr = {https://researchr.org/publication/NoguchiITAKKHAS16},
cites = {0},
citedby = {0},
pages = {132-133},
booktitle = {2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016},
publisher = {IEEE},
isbn = {978-1-4673-9467-3},
}