Testing and Design-for-Testability Techniques for 3D Integrated Circuits

Brandon Noia, Krishnendu Chakrabarty. Testing and Design-for-Testability Techniques for 3D Integrated Circuits. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011. pages 474-479, IEEE Computer Society, 2011. [doi]

@inproceedings{NoiaC11a,
  title = {Testing and Design-for-Testability Techniques for 3D Integrated Circuits},
  author = {Brandon Noia and Krishnendu Chakrabarty},
  year = {2011},
  doi = {10.1109/ATS.2011.67},
  url = {http://doi.ieeecomputersociety.org/10.1109/ATS.2011.67},
  researchr = {https://researchr.org/publication/NoiaC11a},
  cites = {0},
  citedby = {0},
  pages = {474-479},
  booktitle = {Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011},
  publisher = {IEEE Computer Society},
  isbn = {978-1-4577-1984-4},
}