Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo. A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. In Hamid R. Arabnia, editor, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2005, Las Vegas, Nevada, USA, June 27-30, 2005, Volume 2. pages 447-453, CSREA Press, 2005.
@inproceedings{OgasawaraKYSSUNN05,
title = {A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation},
author = {Yoshiyasu Ogasawara and Norito Kato and Masanori Yamato and Mikiko Sato and Koichi Sasada and Kaname Uchikura and Mitaro Namiki and Hironori Nakajo},
year = {2005},
tags = {caching, process modeling},
researchr = {https://researchr.org/publication/OgasawaraKYSSUNN05},
cites = {0},
citedby = {0},
pages = {447-453},
booktitle = {Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2005, Las Vegas, Nevada, USA, June 27-30, 2005, Volume 2},
editor = {Hamid R. Arabnia},
publisher = {CSREA Press},
isbn = {1-932415-59-9},
}