Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo. A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. In Hamid R. Arabnia, editor, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2005, Las Vegas, Nevada, USA, June 27-30, 2005, Volume 2. pages 447-453, CSREA Press, 2005.
Abstract is missing.