Gated Clock Routing Minimizing the Switched Capacitance - researchr publication authors

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Jaewon Oh, Massoud Pedram. Gated Clock Routing Minimizing the Switched Capacitance. In 1998 Design, Automation and Test in Europe (DATE 98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France. pages 692-697, IEEE Computer Society, 1998. [doi]

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