Yusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa. A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI. IEICE Transactions, 91-C(4):655-661, 2008. [doi]
@article{OhtomoKNN08,
title = {A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI},
author = {Yusuke Ohtomo and Hiroshi Koizumi and Kazuyoshi Nishimura and Masafumi Nogawa},
year = {2008},
doi = {10.1093/ietele/e91-c.4.655},
url = {http://dx.doi.org/10.1093/ietele/e91-c.4.655},
tags = {architecture},
researchr = {https://researchr.org/publication/OhtomoKNN08},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {91-C},
number = {4},
pages = {655-661},
}