3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE

Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Seitaro Kawai, Shinji Yamaura, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori. 3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE. In 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014. pages 60-61, IEEE, 2014. [doi]

@inproceedings{OishiYSTKSKKMTK14,
  title = {3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE},
  author = {Kazuaki Oishi and Eiji Yoshida and Yasufumi Sakai and Hideki Takauchi and Yoichi Kawano and Noriaki Shirai and Hideki Kano and Masahiro Kudo and Tomotoshi Murakami and Tetsuro Tamura and Seitaro Kawai and Shinji Yamaura and Kazuo Suto and Hiroshi Yamazaki and Toshihiko Mori},
  year = {2014},
  doi = {10.1109/ISSCC.2014.6757337},
  url = {https://doi.org/10.1109/ISSCC.2014.6757337},
  researchr = {https://researchr.org/publication/OishiYSTKSKKMTK14},
  cites = {0},
  citedby = {0},
  pages = {60-61},
  booktitle = {2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014},
  publisher = {IEEE},
  isbn = {978-1-4799-0918-6},
}